Broadcom has introduced its 3.5D eXtreme Dimension System in Package (3.5D XDSiP) platform for ultra-high-performance processors for AI and HPC workloads. The new platform relies on TSMC's CoWoS and other advanced packaging technologies. It enables chip designers to build system-in-packages (SiPs) of 3D-stacked logic, network and I/O chiplets, and HBM memory stacks. The platform allows for SiPs with up to 6000mm² of 3D-stacked silicon with 12 HBM modules. The first 3.5D XDSiP products are set to arrive in 2026.
Broadcom's 3.5D XDSiP uses TSMC's CoWoS-L packaging technology that offers a maximum interposer size of approximately 5.5 times that of a reticle (about 858 mm^2), or 4719 mm^2 for compute chiplets, I/O chiplets, and up to 12 HBM3/HBM4 packages. To maximize performance, Broadcom suggests disintegrating the design of compute chiplets and stacking one logic chiplet on top of another in a face-to-face (F2F) manner using hybrid copper bonding (HCB).
