Electronic design automation (EDA) tools and third-party IP blocks are ready for TSMC's performance-enhanced N2P and N2X process technologies (2nm-class), the world's largest foundry announced at its European Open Innovation Platform (OIP) forum this week. This allows various chip designers to develop chips based on TSMC's second-gen 2nm-class production nodes, thus taking advantage of nanosheet transistors and low-resistance capacitors.
By now, all major tools from Cadence and Synopsys, as well as simulation and electromigration tools from Siemens EDA and Ansys, are ready for TSMC's N2P fabrication process. These programs have already been certified for the N2P process development kit (PDK) version 0.9, deemed adequate as mass production using this fabrication process is slated for the second half of 2026, about two years from now.
