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FOUND: Kevin zhang - What They Never Told You

Energy use forcing rethink of AI chip design, TSMC says

AI's massive electricity needs are now driving chip development. Energy efficiency is becoming more critical than raw computing power. TSMC, a leading chipmaker, sees customers prioritizing performance gains that use less power. This shift impacts smartphones to AI data centers. New technologies like advanced packaging and chip stacking are key.…

The Economic Times

TSMC, Sony Semiconductor Solutions to establish image sensor joint venture in Kumamoto

TSMC, Sony Semiconductor Solutions to establish image sensor joint venture in Kumamoto

Taiwan Semiconductor Manufacturing and Sony Semiconductor Solutions are joining forces. They will establish a joint venture in Kumamoto, Japan. This partnership will focus on developing and producing advanced image sensors. The collaboration combines Sony's sensor design expertise with TSMC's manufacturing prowess.

The Economic Times

TSMC unveils process technology roadmap through 2029 — A12, A13, N2U announced, A16 slips to 2027

TSMC unveils process technology roadmap through 2029 — A12, A13, N2U announced, A16 slips to 2027

TSMC strengthens its bifurcated process technology development approach with A14, A13, and N2U aimed at client applications and A16, A12, and N2X for high-performance data center designs.

Tom’s Hardware

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Surge AI Quietly Hit $1B Without Outside Money — Now Even VCs Want In

Surge AI stayed under the radar until this summer, when news broke that the company crossed $1 billion in annual revenue without raising any outside capital. The company offers data labeling services used by companies, including Google and OpenAI, helping them train large-scale machine learning models, Inc. reports.

TSMC reiterates it doesn't need High-NA EUV for 1.4nm-class process technology

TSMC reaffirmed that it will not use High-NA EUV lithography for its upcoming A16 and A14 process technologies, as Low-NA EUV tools combined with internal innovations provide sufficient scaling and performance benefits.

Tom’s Hardware

TSMC to open up chip design center in Munich to help local chip developers

TSMC will open its first European chip design center in Munich to support European developers with design technology co-optimization for both mature and advanced nodes.

Tom’s Hardware

TSMC SVP Kevin Zhang opens up on process technology development & evolving demands: Interview

TSMC is evolving its strategy by developing distinct leading-edge process technologies optimized for AI, client, and HPC applications, while maintaining aggressive scaling with innovations like backside power delivery and second-generation nanosheet transistors.

Tom’s Hardware

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TSMC unveils 1.4nm technology: 2nd Gen GAA transistors, full node advantages, coming in 2028

TSMC unveils 1.4nm technology: 2nd Gen GAA transistors, full node advantages, coming in 2028

TSMC unveils its A14 process technology featuring 2nd generation GAA nanosheet transistors and NanoFlex Pro DTCO with production slated for 2028.

Tom’s Hardware

Broadcom unveils gigantic 3.5D XDSiP platform for AI XPUs — 6000mm² of stacked silicon with 12 HBM modules

Broadcom unveils gigantic 3.5D XDSiP platform for AI XPUs — 6000mm² of stacked silicon with 12 HBM modules

Broadcom's 3.5D XDSiP platform for high-performance processors uses TSMC's CoWoS and other packaging technologies to build a system-in-packages comprising 6000mm² of 3D-stacked silicon with 12 HBM modules.

Tom’s Hardware

10 Years Later, the Publisher of the World’s Weirdest Video Games Is Doubling Down

10 Years Later, the Publisher of the World’s Weirdest Video Games Is Doubling Down

Ten years later, the co-founders of Serenity Forge sit down to talk about Doki Doki Literature Club, Roman Sands Re:Build, and others.

TSMC VP says 'I don’t care if Moore’s Law is alive or dead' if technology keeps scaling — 3D chip packaging fuels continued advances

TSMC VP says 'I don’t care if Moore’s Law is alive or dead' if technology keeps scaling — 3D chip packaging fuels continued advances

TSMC's Kevin Zhang states that while Moore's Law's traditional focus on transistor density may be less relevant, TSMC's continual advancements in technology scaling and 2.5D and 3D integration make it more than alive.

Tom’s Hardware

TSMC Offers a Peek at 'Global Gigafab' Process Replication Program

TSMC Offers a Peek at 'Global Gigafab' Process Replication Program

At its European Technology Symposium last week TSMC revealed some of the details about its Global Gigafab Manufacturing program, the company's strategy to replicate its manufacturing processes across its multiple gigafab sites. The need for large-scale multi-national fabs to have a process in place to replicate their facilities is well-documented…

TSMC to Expand Specialty Capacity by 50%, Introduce 4nm N4e Low-Power Node

TSMC to Expand Specialty Capacity by 50%, Introduce 4nm N4e Low-Power Node

With all the new fabs being built in Germany and Japan, as well as the expansion of production capacity in China, TSMC is planning to extend its production capacity for specialty technologies by 50% by 2027. As disclosed by the company during its European Technology Symposium this week, TSMC expects…

TSMC's System-on-Wafer Platform Goes 3D: CoW-SoW Stacks Up the Chips

TSMC's System-on-Wafer Platform Goes 3D: CoW-SoW Stacks Up the Chips

TSMC has been offering its System-on-Wafer integration technology, InFO-SoW, since 2020. For now, only Cerebras and Tesla have developed wafer scale processor designs using it, as while they have fantastic performance and power efficiency, wafer-scale processors are extremely complex to develop and produce. But TSMC believes that not only will…

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Tom’s Hardware

TSMC says it doesn't need High-NA EUV chipmaking tools for 1.6nm-class node, but Intel has championed the tech

TSMC says it will not need a high-NA litho tool for its A16 technology but will keep exploring it for A16 and beyond.

TSMC Preps Cheaper 4nm N4C Process For 2025, Aiming For 8.5% Cost Reduction

While the bulk of attention on TSMC is aimed at its leading-edge nodes, such as N3E and N2, loads of chips will continue to be made using more mature and proven process technologies for years to come. Which is why TSMC has continued to refine its existing nodes, including its…

SK Hynix and TSMC Team Up for HBM4 Development

SK hynix and TSMC announced early on Friday that they had signed a memorandum of understanding to collaborate on developing the next-generation HBM4 memory and advanced packaging technology. The initiative is designed to speed up the adoption of HBM4 memory and solidify SK hynix's and TSMC's leading positions in high-bandwidth…

Marvell's 2nm IP Platform Enables Custom Silicon for Datacenters

Marvell this week introduced its new IP technology platform specifically tailored for custom chips for accelerated infrastructure made on TSMC's 2nm-class process technologies (possibly including N2 and N2P). The platform includes technologies essential for developing cloud-optimized accelerators, Ethernet switches, and digital signal processors. "The 2nm platform will enable Marvell to…

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